Exemplary embodiments of the present invention relate to a test control circuit, and more particularly, to a multi-bit test control circuit which tests plural banks at the same time to reduce a test time.
A semiconductor device may perform a test operation while activating all banks at the same time. However, in order to test a bank interleaving operation or reduce a peak current of power due to the activation of all banks, a single bank is activated in a test operation and a test data of the activated bank is outputted and investigated.
FIG. 1 is a configuration diagram illustrating a conventional semiconductor device which includes four banks and performs a multi-bit test operation.
Referring to FIG. 1, when four banks BK0 to BK3 are provided within a semiconductor device, each bank compresses data and performs a test thereon. When a bank interleaving operation is performed in a multi-bit test operation, one bank is selected and output data of the banks except for the selected bank are set to a certain logic level.
As one example, when a read operation is performed on the bank BK0 in the multi-bit test operation, the output signals of the remaining banks BK1 to BK3 are set to a logic high level. Therefore, test data DATA_BK1 to DATA_BK3 of the banks BK1 to BK3 are set so that output signal of driving units TGO_DRV BK1 to TGO_DRV BK3 can be in a logic high level. The driving unit TGO_DRV BK0 which reads test data DATA_BK0 of the bank BK0 can output data according to the read operation on the bank BK0.
As illustrated in a timing diagram of FIG. 2, control signals IOFIX_BK1 to IOFIX_BK3 for reading data of the banks BK1 to BK3 are controlled to be in a logic high level, unlike a control signal IOFIX_BK0 for reading data of the bank BK0. Through such a control operation, the data of the bank BK0 is read out.
FIG. 3 is a block diagram illustrating the driving unit shown in FIG. 1. Specifically, the driving units TGO_DRV BK0 to TGO_DRV BK1 corresponding to the banks BK0 to BK1 are illustrated as an example. FIG. 4 is a configuration diagram illustrating a circuit for generating a control signal for the bank BK0 according to the conventional multi-bit test operation.
According to the configurations of FIGS. 3 and 4, the control signal IOFIX is set to a logic low level in a typical multi-bit test operation. At this time, when the control signal IOFIX is in a logic low level, a data fixing unit DATA_IOFIX outputs data information, i.e., DATA_BK0 or DATA_BK1, to a driving unit TGO_DRV as it is. Meanwhile, when the control signal IOFIX is in a logic high level, the data fixing unit DATA_IOFIX outputs a logic high level signal to the driving unit TGO_DRV regardless of the data information.
When a signal IOSTB_TGO inputted to the driving unit TGO_DRV becomes a logic high level, the driving unit TGO_DRV outputs information TGO_DATA from the data fixing unit DATA_IOFIX. Output information of the driving unit TGO_DRV is outputted to the outside of the semiconductor device through a data output pad DQ. Therefore, in the typical multi-bit test operation, data is read from each bank. When the signal IOSTB_TGO is enabled, read data of all banks are outputted at the same time.
However, when the bank interleaving operation is performed, for example, only the bank corresponding to a read command outputs data and, for example, only the signal IOSTB_TGO inputted to the corresponding bank is enabled. In the remaining banks except for the corresponding bank, the control signal IOFIX is set to a logic high level and thus the output signals of the data fixing units DATA_IOFIX are set to a logic high level as described above. The signal IOSTB_TGO inputted to the remaining banks is also disabled, and the output signals of the driving units TGO_DRV are set to a logic high level.
Meanwhile, as illustrated in FIG. 4, the control signal IOFIX and the signal IOSTB_TGO are generated in order to control the multi-bit test operation of each bank. The control signal IOFIX is a signal which determines whether to output the data information of the data fixing unit. That is, the data information is outputted or a set signal of a logic high level is outputted regardless of the data information in response to the control signal IOFIX. The control signal IOFIX signal is generated by combining a multi-bit test mode signal MULTI_BIT_TM indicating a bank interleaving multi-bit test operation mode and a source signal IOFIX_source having a low pulse (tIOFIX duration) only in the read operation. Also, the signal IOSTB_TGO is generated by delaying a signal PINB by a certain time. The PINB signal is a source signal of all signals inputted to each bank.
As discussed above, various source signals such as the signals IOFIX_source PINB are used to control the conventional multi-bit test operation, and thus signal lines, control logics, and so on for these signals are also used. Moreover, due to the use of these signal lines, it is difficult to secure a margin between signals.